The present disclosure relates to dynamic hard error detection, and in particular to testing functionality of a circuit by performing a test of the circuit while applying stress to the circuit.
Physical structures on computer chips degrade with age. Electromigration, thermal stress and other conditions that increase or self-perpetuate over time may result in hard errors in logic, latches, registers or arrays on the chip, such as stuck-at faults or delays. In conventional chips, detecting hard errors is costly, because it requires either detection logic added to the chip, requiring chip area and power, or it consumes resources resulting in degraded performance or energy-consumption of the chip.
In addition, when a chip is manufactured, the chip may be tested to determine acceptable ranges of operation, then a margin may be added to one acceptable operating level and the chip may be programmed or designed to operate outside the margin to account for anticipated degradation of chip performance during the life of a chip. For example, a chip may be designed to operate below its optimal frequency based on estimates that over time the optimal frequency will drift downward.